3 ISA Fundamentals & Instruction Formats

1. What Is an ISA?

• Instruction Set Architecture (ISA): the contract between hardware and software
  • Defines operations, data types, registers, memory model, and binary encoding
  • Abstraction layers:
    1. High-level language
    2. Assembly language
    3. Machine code (ISA)
    4. Microarchitecture (implementation)

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2. RISC-V Overview (RV32I)

• RISC vs. CISC: simple, fixed-length instructions vs. complex variable-length
• RV32I features:
  • 32-bit instructions, registers, addresses
  • 32 general-purpose registers: x0…x31 (x0 is hardwired to 0)
  • Load/store architecture (no memory-to-memory ALU)

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3. 32-bit Instruction Formats

All instructions are 32 bits wide; different formats pack fields differently.

Format	Name	Fields	Use cases
R	Register	funct7 │ rs2 │ rs1 │ funct3 │ rd │ opcode	add, sub, and
I	Immediate	imm[11:0] │ rs1 │ funct3 │ rd │ opcode	addi, lw, jalr
S	Store	imm[11:5] │ rs2 │ rs1 │ funct3 │ imm[4:0] │ opcode	sw, sb
B	Branch	imm[12] │ imm[10:5] │ rs2 │ rs1 │ funct3 │ imm[4:1] │ imm[11] │ opcode	beq, bne
U	Upper	imm[31:12] │ rd │ opcode	lui, auipc
J	Jump	imm[20] │ imm[10:1] │ imm[11] │ imm[19:12] │ rd │ opcode	jal

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3.1 R-Type (Register)

| funct7 (7) │ rs2 (5) │ rs1 (5) │ funct3 (3) │ rd (5) │ opcode (7) |

• Operation: rd ← rs1 OP rs2
• Example: add x5, x6, x7

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3.2 I-Type (Immediate)

| imm[11:0] (12) │ rs1 (5) │ funct3 (3) │ rd (5) │ opcode (7) |

• Operation: rd ← rs1 OP imm or load rd ← M[rs1 + imm]
• Sign-extend imm[11] to 32 bits
• Example: addi x10, x0, 42 # x10 ← 42

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3.3 S-Type (Store)

'| imm[11:5] (7) │ rs2 (5) │ rs1 (5) │ funct3 (3) │ imm[4:0] (5) │ opcode (7) |'

• Operation: M[rs1 + imm] ← rs2
• Immediate: concat imm[11:5]∥imm[4:0], then sign-extend

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3.4 B-Type (Branch)

| imm[12] (1) │ imm[10:5] (6) │ rs2 (5) │ rs1 (5) │ funct3 (3) │ imm[4:1] (4) │ imm[11] (1) │ opcode (7) |

• Branch target: target = PC + SE(imm[12] imm[11] imm[10:5] imm[4:1] 0)
• Example: beq x1, x2, offset

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3.5 U-Type (Upper Immediate)

| imm[31:12] (20) │ rd (5) │ opcode (7) |

• Operation: rd ← imm[31:12] << 12
• Use: loading 20-bit constants (lui), PC-relative (auipc)

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3.6 J-Type (Jump)

| imm[20] (1) │ imm[10:1] (10) │ imm[11] (1) │ imm[19:12] (8) │ rd (5) │ opcode (7) |

• Jump target: target = PC + SE(imm[20] imm[19:12] imm[11] imm[10:1] 0)

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4. Register File & ABI Names

• 32 registers, each 32 bits wide
• x0 is always zero
• ABI names:
  • x1 = ra (return address)
  • x2 = sp (stack pointer)
  • x5–x7 = t0–t2 (temporaries)
  • x10–x17 = a0–a7 (arguments/returns)

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5. Example: Assembling sw x8, 16(x9)

1. opcode = `0100011`
2. funct3 = `010` (store word)
3. rs1 = `x9` → `01001`
4. rs2 = `x8` → `01000`
5. imm = 16 → `00000010000`₂ → `imm[11:5]=0000001`, `imm[4:0]=0000`
6. Pack fields into 32 bits → machine code

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