Lecture 1: Course Overview & Basic CPU Concepts
- Abstraction layers: high-level code → assembly → machine code → microarchitecture
- Processor architectures: Harvard vs. von Neumann, trade-offs in speed vs. flexibility
- IC cost factors: dies per wafer, yield, cost per die formula
- CPU time breakdown: Instruction Count × CPI × Cycle Time
- CPI factors: instruction mix, hardware implementation, pipeline stalls
- Amdahl’s Law: overall speedup = 1/((1-f) + f/S)
Lecture 3: RISC-V ISA Fundamentals
- ISA roles: defines registers, instruction formats, addressing modes
- Instruction formats: R, I, S, B, U, J type field layouts
- Register conventions: x0–x31, ABI names (ra, sp, t0–t6, a0–a7)
Lecture 4: Control Flow & Addressing Modes
- Branches (B-type): beq, bne, blt/bltu, bge/bgeu; PC update logic
- Jumps: jal (J-type) and jalr (I-type), link register behavior
- Function call conventions: stack frame, prologue/epilogue, ra/sp usage
- Addressing modes: register-immediate, PC-relative, U-type immediates
Lecture 5: Control Unit & ALU Control
- Main Control outputs: RegWrite, MemRead/Write, MemToReg, ALUSrc, Branch, Jump, ALUOp
- ALU Control input mapping: ALUOp + funct7/3 → exact ALU operation
- Control signal patterns: R-type vs. load/store vs. branch vs. jump
Lecture 6: End-to-End Case Studies
- Lifecycle steps: Fetch → Decode → Execute → Memory → Write-back → PC update
- Case studies: R-type add, lw, sw, beq, jal walkthroughs
- Control signals in action: how each signal steers datapath components
Lecture 7: Single-Cycle Datapath
- 5 stages in one cycle: IF, ID, EX, MEM, WB
- Pipeline registers: IF/ID, ID/EX, EX/MEM, MEM/WB in single-cycle concept
- Data flow per instruction type: R/I/Store/Branch/Jump sequences
- Critical path & cycle time: slowest combined stage delay
Lecture 8: Pipelining & Hazards
- Pipeline benefits: overlap stages for increased throughput (ideal CPI ≈1)
- Hazard types: structural, data (RAW), control hazards
- Resolution techniques: forwarding, stalls/bubbles, branch prediction, flush
- Performance impact: added CPI = 1 + stalls per instruction