library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity shift_register is Port ( d : in STD_LOGIC_VECTOR (3 downto 0); clk : in STD_LOGIC; load, shift : in STD_LOGIC; q : out STD_LOGIC_VECTOR (3 downto 0)); end shift_register;
architecture Behavioral of shift_register is signal temp : STD_LOGIC_VECTOR(3 downto 0); begin process(clk) begin if rising_edge(clk) then if load = ‘1’ then temp ⇐ d; elsif shift = ‘1’ then temp ⇐ ‘0’ & temp(3 downto 0); end if; end if; end process;
q <= temp;
end Behavioral;