All flip flops are just latches that are activated by an edge
Flip flop/Latches
Bistable
they remember the previous input and keep it until another input is entered
These are sequential circuits
SR Flip-Flop
it will output 1 if set is 1 and will stay 1 until reset is pressed
when reset is active it turns off
it latches
Gated SR
Much like the SR flip flop, but instead it now has a and gate that is the “enable” pin so it would output nothing unless
D Flip flop
it has reset, set, clock and data
Basically set and reset are asynchronous so it has priority over data and clock, whereas data and clock must be in sync like data 1 and then has to wait for clock 1 to turn on
A major down side to D flip flop is that when set and reset are enabled it enters an invalid state
JK flipflop
Instead of haveing a clock/enable pin in a 2 input and gate it uses a 3 input nand gate
