Formula Sheet

1. CPU Performance

• Clock rate vs. cycle time
  $\text{Clock rate (Hz)}=\frac{1}{\text{Clock cycle time (s)}}$

• Clock cycles
  $\text{Clock cycles}=\text{Instruction count}\times \text{CPI}$

• CPU execution time
  $T_{\text{exec}}=\text{Clock cycles}\times \text{Clock cycle time}=\frac{\text{Instruction count}\times \text{CPI}}{\text{Clock rate}}$

2. Instruction Count Factors

• Instruction count depends on:
  • Program algorithm
  • ISA complexity
  • Compiler optimizations

• Average CPI depends on hardware design and instruction mix

3. Amdahl’s Law

• Overall speedup when a fraction $f$ of execution is improved by $S$:
  ${\text{Speedup}}_{\text{total}}=\frac{1}{(1-f)+\frac{f}{S}}$

4. Pipeline Performance

• Ideal CPI = 1 (one instruction completed per cycle after pipeline fill)
• Actual CPI = $1+\text{Stall cycles per instruction}$
• Pipeline speedup approx:
  $\text{Speedup}\approx \frac{\text{Single-cycle IPC}}{\text{Pipeline CPI}}$

5. Memory & Cost

• Cost per die
  $\text{Cost per die}=\frac{\text{Cost per wafer}}{\text{Dies per wafer}\times \text{Yield}}$

• Dies per wafer (approx.)
  $\frac{\pi (\text{wafer radius}{)}^2}{\text{die area}}$

• Yield (two-parameter model)
  $\text{Yield}=\frac{1}{(1+\frac{\text{Defects per area}\times \text{Die area}}{\alpha }{)}^{\alpha }}$

6. Branch Penalty

• Average CPI with branches
  ${\text{CPI}}_{\text{avg}}={\text{CPI}}_{\text{base}}+\text{Branch frequency}\times \text{Branch penalty}$

7. Address Translation (if covered)

• Virtual to physical address:
  $\text{Physical}=\text{VPN}\parallel \text{Offset}$
• TLB hit rate affects effective memory access time

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